1. Field of the Invention
The present invention relates to a static random access memory (SRAM), and more particularly to a six transistors static random access memory (6T-SRAM) cell with increased stability and increased writing speed.
2. Description of the Prior Art
An embedded static random access memory (SRAM) comprises a logic circuit and a static random access memory connected to the logic circuit. SRAM is a kind of volatile memory cell, which means it preserves data only while power is continuously applied. SRAM is built of cross-coupled inverters that store data during the time that power remains applied, unlike dynamic random access memory (DRAM) that needs to be periodically refreshed. Because of its high access speed, SRAM is also used in computer systems as a cache memory.
Referring to FIG. 1, FIG. 1 illustrates a circuit diagram of a conventional six-transistor SRAM (6T-SRAM) cell. The device includes at least one SRAM cell, each SRAM cell including a six-transistor SRAM (6T-SRAM) cell 10.
Each 6T-SRAM cell 10 is composed of a first pull-up transistor 12, a second pull-up transistor 14, and a first pull-down transistor 16, a second pull-down transistor 18, a first access transistor 20 and a second access transistor 21. These six devices (transistors) constitute a set of flip-flops. The first and the second pull-up transistors 12 and 14, and the first and the second pull-down transistors 16 and 18 constitute a latch circuit 22 that stores data in the storage nodes 24 and 26. Since the first and the second pull-up transistors 12 and 14 act as power load devices, they can be replaced by resistors. Under this circumstance, the static random access memory becomes a four-transistor SRAM (4T-SRAM). In addition, the first and the second pull-up transistors 12 and 14 preferably share a source/drain region and electrically connect to a voltage source (voltage node) Vcc, and the first and the second pull-down transistors 16 and 18 share a source/drain region and electrically connect to a voltage source (voltage node) Vss.
Preferably, the first and the second pull-up transistors 12 and 14 of the 6T-SRAM cell 10 are composed of p-type metal oxide semiconductor (PMOS) transistors, and the first and the second pull-down transistors 16 and 18, the first access transistors 20 and the second access transistors 21 are composed of n-type metal oxide semiconductor (NMOS) transistors. The first pull-up transistor 12 and the first pull-down transistor 16 constitute an inverter, which further form a series circuit 28. One end of the series circuit 28 is connected to a voltage source Vcc and the other end of the series circuit 28 is connected to a voltage source Vss. Similarly, the second pull-up transistor 14 and the second pull-down transistor 18 constitute another inverter and a series circuit 30. One end of the series circuit 30 is connected to the voltage source Vcc and the other end of the series circuit 30 is connected to the voltage source Vss. The two inverters are cross-coupled to each other to store data.
The storage node 24 is connected to the respective gates of the second pull-down transistor 18 and the second pull-up transistor 14. The storage node 24 is also connected to the drains of the first pull-down transistor 16, the first pull-up transistor 12 and the first access transistor 20. Similarly, the storage node 26 is connected to the respective gates of the first pull-down transistor 16 and first the pull-up transistor 12. The storage node 26 is also connected to the drains of the second pull-down transistor 18, the second pull-up transistor 14 and the second access transistor 21. The gates of the first access transistor 20 and the second access transistor 21 are respectively coupled to one word line 32; the sources of the first access transistor 20 and the second access transistor 21 are respectively coupled to a first bit line 34 and a second bit line 36.